Various charge refreshment techniques are well known in the art which are useful for refreshing charge packets serially transferred in a charge coupled device (CCD) and which dissipate in amplitude and definition due to the limited charge transfer efficiency and leakage current of the charge coupled device. Such charge refresher devices introduce a charge packet of superior definition and amplitude in place of the dissipated charge packet, and the refreshed charge packet continues to be transferred serially in the CCD register in place of the original dissipated charge packet. Prior art charge refresher devices include bistable latches which compared the original charge packet with a reference level to determine whether or not the charge packet represents a one or a zero, this comparison determining which of two states the latch assumes. The output of the latch either generates a logic 1, causing a refreshed charge packet to be injected into the charge coupled device in place of the original packet, or a logic 0, in which no charge is injected into the charge coupled device. The charge refresher must compare a serial succession of charge packets in a periodic manner to generate a corresponding serial succession of output refreshed charge packets injected into the charge coupled device. One problem with this type of charge refresher is that the output nodes and the feedback nodes of the bistable latch are shared so that the output current is divided between the output and the feedback, thus reducing the output voltage and reducing the speed of the device. Furthermore, such devices typically consume dc electrical power when latched. One solution to these problems is the charge coupled device charge comparator refresher of the Hamilton and Carrison patent application referenced above, in which charge refreshment is performed without requiring a bistable latch or similar active device, thus eliminating the problem of dividing current between output and feedback nodes and the problem of high dc electrical power consumption.
However, unless a bistable latch or equivalent device is used, the speed of the charge refresher circuit is reduced, since the switching speed of a bistable latch is typically greater than the speed of the comparator refresher of the Hamilton and Carrison Application.